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SAC
2010
ACM
13 years 8 months ago
Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints
Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (P...
Pavel Ghosh, Arunabha Sen
DAC
2009
ACM
14 years 8 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
ICCD
2007
IEEE
179views Hardware» more  ICCD 2007»
14 years 4 months ago
Energy-aware co-processor selection for embedded processors on FPGAs
In this paper, we present co-processor selection problem for minimum energy consumption in hw/sw co-design on FPGAs with dual power mode. We provide theoretical analysis for the p...
Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Suda...
PERCOM
2008
ACM
14 years 7 months ago
Enabling Deliberate Design for Energy Management in Pervasive Systems
This paper argues for explicit consideration of data fidelity during development of context-aware systems. Increasing the amount of data captured, stored, and distributed does not ...
Angela Dalton, Carla Schlatter Ellis, Christine Ju...
ISPAN
2009
IEEE
14 years 2 months ago
Chaining Clock Synchronization: An Energy-Efficient Clock Synchronization Scheme for Wireless Sensor Networks
— Since WSNs have restricted energy sources, the energy efficiency of a synchronization scheme is as important as the accuracy of a clock. To accomplish both the energy efficienc...
Sang Hoon Lee, Lynn Choi