285 search results - page 16 / 57 » Cell architecture for nanoelectronic design |
ISMVL
2010
IEEE
14 years 13 days ago
2010
IEEE
—Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is bas...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
this paper proposes a novel Process Variation Aware SRAM architecture designed to inherently support voltage scaling. The peripheral circuitry of the SRAM is modified to selectivel...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
The Cell processor offers substantial computational power which can be effectively utilized only if application design and implementation are tuned to the Cell architecture. In th...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
We discover significant value-dependent programming energy variations in multi-level cell (MLC) flash memories, and introduce an energy-aware data compression method that minimize...