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ARITH
2005
IEEE
14 years 1 months ago
The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
Silvia M. Müller, Christian Jacobi 0002, Hwa-...
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
13 years 11 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
CCR
2010
162views more  CCR 2010»
13 years 7 months ago
Radio resource management considerations for LTE Femto cells
Femtocell access points (FAPs), also popularly known as Home Base Stations, are small base stations for use within indoor environments to improve coverage and capacity. FAPs have ...
Parag Kulkarni, Woon Hau Chin, Tim Farnham
ICS
2009
Tsinghua U.
14 years 2 months ago
High-performance regular expression scanning on the Cell/B.E. processor
Matching regular expressions (regexps) is a very common workload. For example, tokenization, which consists of recognizing words or keywords in a character stream, appears in ever...
Daniele Paolo Scarpazza, Gregory F. Russell
HPCA
2011
IEEE
12 years 11 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...