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» Cell architecture for nanoelectronic design
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DAC
2010
ACM
13 years 11 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
SIGCOMM
2009
ACM
14 years 2 months ago
mango: low-cost, scalable delivery of rich content on mobiles
We present mango, a low-cost and highly scalable content-delivery service for mobile phones. The service is targeted at emerging countries such as India where users are highly pri...
Ankur Jain, Sharad Jaiswal, Anirban Majumder, K. V...
ICAI
2008
13 years 9 months ago
Behavior-based Perceptual Navigation for Semi-Autonomous Wheelchair Operations
Abstract-- This paper describes an overview of our semiautonomous (SA) wheelchair prototype and emphasizes the design of the perceptual navigation system. The goal of our project i...
Hajime Uchiyama, Walter D. Potter
CF
2005
ACM
13 years 9 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
VLSID
2007
IEEE
146views VLSI» more  VLSID 2007»
14 years 7 months ago
Architecting Microprocessor Components in 3D Design Space
Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional ...
Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang 0004,...