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» Cell delay analysis based on rate-of-current change
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DATE
2002
IEEE
102views Hardware» more  DATE 2002»
14 years 19 days ago
Library Compatible Ceff for Gate-Level Timing
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...
Bernard N. Sheehan
ICPADS
2005
IEEE
14 years 1 months ago
Delay-Energy Aware Routing Protocol for Sensor and Actor Networks
We present a novel Delay-Energy Aware Routing Protocol (DEAP) for for heterogeneous sensor and actor networks. DEAP enable a wide range of tradoffs between delay and energy consum...
Arjan Durresi, Vamsi Paruchuri, Leonard Barolli
ASPDAC
2005
ACM
127views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Clock network minimization methodology based on incremental placement
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...
DATE
2010
IEEE
178views Hardware» more  DATE 2010»
14 years 23 days ago
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
—With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits...
Shrikanth Ganapathy, Ramon Canal, Antonio Gonz&aac...
BMCBI
2008
102views more  BMCBI 2008»
13 years 7 months ago
Significance analysis of microarray for relative quantitation of LC/MS data in proteomics
Background: Although fold change is a commonly used criterion in quantitative proteomics for differentiating regulated proteins, it does not provide an estimation of false positiv...
Bryan A. P. Roxas, Qingbo Li