Sciweavers

850 search results - page 115 / 170
» Certification of System Architecture Dependability
Sort
View
DSD
2004
IEEE
136views Hardware» more  DSD 2004»
15 years 9 months ago
FPGA Based Design of the Railway's Interlocking Equipments
This paper describes the architecture of a safety system of the railway's interlocking equipment, which has been developed for Czech railways. The system will be used for the...
Radek Dobias, Hana Kubatova
JTRES
2010
ACM
15 years 6 months ago
The embedded Java benchmark suite JemBench
Requirements to embedded systems increase steadily. In parallel, also the performance of the processors used in these systems is improved leading to multithreaded and/or multicore...
Martin Schoeberl, Thomas B. Preußer, Sascha ...
CIA
2000
Springer
15 years 10 months ago
Towards Information Agent Interoperability
Abstract. Currently, many kinds of information agents for di erent purposes exist. However, agents from di erent systems are still unable to cooperate, even if they accurately foll...
Stefan Haustein, Sascha Lüdecke
DAC
2007
ACM
16 years 7 months ago
Shared Resource Access Attributes for High-Level Contention Models
Emerging single-chip heterogeneous multiprocessors feature hundreds of design elements contending for shared resources, making it difficult to isolate performance impacts of indiv...
Alex Bobrek, JoAnn M. Paul, Donald E. Thomas
ICS
2009
Tsinghua U.
16 years 23 days ago
Performance modeling and automatic ghost zone optimization for iterative stencil loops on GPUs
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...
Jiayuan Meng, Kevin Skadron