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» Challenges in Physical Chip Design
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MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
14 years 2 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
ASPLOS
2004
ACM
14 years 2 months ago
Continual flow pipelines
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkar...
EMSOFT
2004
Springer
14 years 2 months ago
A model-based approach to integrating security policies for embedded devices
Embedded devices like smart cards can now run multiple interacting applications. A particular challenge in this domain is to dynamically integrate diverse security policies. In th...
Michael McDougall, Rajeev Alur, Carl A. Gunter
CGO
2010
IEEE
14 years 2 months ago
Contention aware execution: online contention detection and response
Cross-core application interference due to contention for shared on-chip and off-chip resources pose a significant challenge to providing application level quality of service (Qo...
Jason Mars, Neil Vachharajani, Robert Hundt, Mary ...
MMB
2010
Springer
194views Communications» more  MMB 2010»
14 years 1 months ago
Searching for Tight Performance Bounds in Feed-Forward Networks
Abstract. Computing tight performance bounds in feed-forward networks under general assumptions about arrival and server models has turned out to be a challenging problem. Recently...
Andreas Kiefer, Nicos Gollan, Jens B. Schmitt