658 search results - page 14 / 132 » Challenges in Physical Chip Design |
CCE
2007
13 years 10 months ago
2007
: The concept of Virtual Organisation (VO) offers various solutions to management, collaboration and coordination issues important for distributed collaborating teams. Deployment o...
ICCAD
2000
IEEE
14 years 1 months ago
2000
IEEE
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
SBCCI
2005
ACM
14 years 2 months ago
2005
ACM
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
VLSID
2009
IEEE
14 years 9 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
TCAD
2008
13 years 8 months ago
2008
Physical synthesis tools are responsible for achieving timing closure. Starting with 130nm designs, multiple cycles are required to cross the chip, making latch placement critical...