658 search results - page 16 / 132 » Challenges in Physical Chip Design |
CAINE
2003
13 years 10 months ago
2003
Scan based or Line Sweep methods are a traditional mechanism to traverse the physical layout, or artwork of a microchip. These traversals are incremental in nature. They typically...
HPCA
2008
IEEE
14 years 9 months ago
2008
IEEE
We apply Amdahl's Law to multicore chips using symmetric cores, asymmetric cores, and dynamic techniques that allows cores to work together on sequential execution. To Amdahl...
ISLPED
1999
ACM
14 years 29 days ago
1999
ACM
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
PARA
1998
Springer
14 years 26 days ago
1998
Springer
Abstract. Ahardware and software environment with performance above 1 Tera ops (teracomputing) is presently required to face the leading computational challenges not only in fundam...
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
Supercomputers are increasingly complex systems merging conventional microprocessors with system on a chip level designs that provide the network interface and router. At Sandia N...