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» Challenges in Physical Chip Design
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GLVLSI
2006
IEEE
101views VLSI» more  GLVLSI 2006»
14 years 2 months ago
Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance
Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include interand intra-die variations of geometries, as well as...
Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, ...
ASYNC
2003
IEEE
72views Hardware» more  ASYNC 2003»
14 years 2 months ago
SNAP: A Sensor-Network Asynchronous Processor
We present a Sensor-Network Asynchronous Processor (SNAP), which we have designed to be both a processor core for a sensor-network node and a component of a chip multiprocessor, t...
Clinton Kelly IV, Virantha N. Ekanayake, Rajit Man...
JSA
2008
94views more  JSA 2008»
13 years 8 months ago
Energy reduction through crosstalk avoidance coding in networks on chip
Commercial designs are currently integrating from 10 to 100 embedded processors in a single system on chip (SoC) and the number is likely to increase significantly in the near fut...
Partha Pratim Pande, Amlan Ganguly, Haibo Zhu, Cri...
GLVLSI
1998
IEEE
124views VLSI» more  GLVLSI 1998»
14 years 29 days ago
Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally u...
Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. ...
ICCAD
2008
IEEE
103views Hardware» more  ICCAD 2008»
14 years 5 months ago
Hardware protection and authentication through netlist level obfuscation
—Hardware Intellectual Property (IP) cores have emerged as an integral part of modern System–on–Chip (SoC) designs. However, IP vendors are facing major challenges to protect...
Rajat Subhra Chakraborty, Swarup Bhunia