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» Challenges in Physical Chip Design
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VLSID
2002
IEEE
138views VLSI» more  VLSID 2002»
14 years 9 months ago
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
Haris Lekatsas, Jörg Henkel
DATE
2010
IEEE
142views Hardware» more  DATE 2010»
14 years 1 months ago
Testing TSV-based three-dimensional stacked ICs
To meet customer’s product-quality expectations, each individual IC needs to be tested for manufacturing defects incurred during its many high-precision, and hence defect-prone ...
Erik Jan Marinissen
GI
2004
Springer
14 years 2 months ago
Towards a Framework and a Design Methodology for Autonomic Integrated Systems
: The transition from microelectronics to nanoelectronics reaches physical limits and results in a paradigm shift in the design and fabrication of electronic circuits. The conserva...
Andreas Herkersdorf, Wolfgang Rosenstiel
MOBIHOC
2008
ACM
14 years 8 months ago
An O(log n) dominating set protocol for wireless ad-hoc networks under the physical interference model
Dealing with interference is one of the primary challenges to solve in the design of protocols for wireless ad-hoc networks. Most of the work in the literature assumes localized o...
Christian Scheideler, Andréa W. Richa, Paol...
BIRTHDAY
2007
Springer
14 years 21 days ago
Deriving Specifications for Systems That Are Connected to the Physical World
Well understood methods exist for developing programs from formal specifications. Not only do such methods offer a precise check that certain sorts of deviations from their specifi...
Cliff B. Jones, Ian J. Hayes, Michael A. Jackson