658 search results - page 42 / 132 » Challenges in Physical Chip Design |
SAC
2006
ACM
14 years 2 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
ET
2002
13 years 8 months ago
2002
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
ISLPED
2004
ACM
14 years 2 months ago
2004
ACM
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectur...
MEMOCODE
2007
IEEE
14 years 3 months ago
2007
IEEE
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
MASCOTS
2007
2007
A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization
13 years 10 months ago
—Advances in semiconductor technology, has enabled designers to put complex, massively parallel multiprocessor systems on a single chip. Network on Chip (NoC) that supports high ...