658 search results - page 62 / 132 » Challenges in Physical Chip Design |
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
— Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architec...
SAMOS
2005
Springer
14 years 2 months ago
2005
Springer
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chi...
DATE
2004
IEEE
14 years 15 days ago
2004
IEEE
When an application or external environmental conditions cause a chip's cooling capacity to be exceeded, dynamic thermal management (DTM) dynamically reduces the power densit...
JSA
2007
2007
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
13 years 8 months ago
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Ch...
JETC
2008
13 years 7 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...