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» Challenges in Physical Chip Design
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DAC
2006
ACM
14 years 9 months ago
Scheduling-based test-case generation for verification of multimedia SoCs
Multimedia SoCs are characterized by a main controller that directs the activity of several cores, each of which is in charge of a stage in the processing of a media stream. The v...
Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ron...
ASPDAC
2007
ACM
144views Hardware» more  ASPDAC 2007»
14 years 24 days ago
Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method
With semiconductor fabrication technologies scaled below 100 nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a nu...
Alexander V. Mitev, Michael Marefat, Dongsheng Ma,...
DAC
2005
ACM
13 years 10 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
14 years 1 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi
JSAC
2007
133views more  JSAC 2007»
13 years 8 months ago
On broadcasting with cooperative diversity in multi-hop wireless networks
Abstract— Cooperative diversity facilitates spatio-temporal communications without requiring the deployment of physical antenna arrays. While physical layer studies on cooperativ...
Gentian Jakllari, Srikanth V. Krishnamurthy, Micha...