280 search results - page 15 / 56 » Challenges in exploitation of loop parallelism in embedded a... |
RSP
2006
IEEE
14 years 2 months ago
2006
IEEE
Embedded real-time multimedia applications usually imply data parallel processing. SIMD processors embedded in SOCs are cost-effective to exploit the underlying parallelism. Howev...
CGO
2008
IEEE
14 years 2 months ago
2008
IEEE
Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the ...
SC
1992
ACM
14 years 16 days ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
MICRO
2000
IEEE
13 years 8 months ago
2000
IEEE
High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their de...
EUROPAR
2006
Springer
14 years 4 days ago
2006
Springer
Abstract. This paper presents a study of performance optimization of dense matrix multiplication on IBM Cyclops-64(C64) chip architecture. Although much has been published on how t...