280 search results - page 26 / 56 » Challenges in exploitation of loop parallelism in embedded a... |
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
— The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing paral...
ICCS
2005
Springer
14 years 2 months ago
2005
Springer
Cray X1 Fortran and C/C++ compilers provide a number of loop transformations, notably vectorization and multistreaming, in order to exploit the multistreaming processor (MSP) hard...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
One of the primary challenges in embedded system design is designing the memory hierarchy and restructuring the application to take advantage of it. This task is particularly impo...
ARC
2007
Springer
14 years 14 days ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
ICMCS
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper, a high-level optimization methodology is applied for the implementation of the well-known Convolutional Face Finder (CFF) algorithm for real-time applications on ce...