197 search results - page 12 / 40 » Characterizing processor architectures for programmable netw... |
FPL
2006
Springer
13 years 11 months ago
2006
Springer
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
IPPS
2003
IEEE
14 years 25 days ago
2003
IEEE
Clusters of PC containing mostly general purpose hardware have become more and more usable for high performance computing tasks in the past few years. Clustering existing systems ...
FPL
2006
Springer
13 years 11 months ago
2006
Springer
Multi-processor architectures have gained interest recently because of their ability to exploit programmable silicon parallelism at acceptable power-efficiency figures. Despite th...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...