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ANCS
2005
ACM
14 years 1 months ago
Gigabit routing on a software-exposed tiled-microprocessor
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we presen...
Umar Saif, James W. Anderson, Anthony Degangi, Ana...
ISCA
1998
IEEE
114views Hardware» more  ISCA 1998»
13 years 11 months ago
Tempest and Typhoon: User-Level Shared Memory
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...
Steven K. Reinhardt, James R. Larus, David A. Wood
ASPLOS
2009
ACM
14 years 8 months ago
StreamRay: a stream filtering architecture for coherent ray tracing
The wide availability of commodity graphics processors has made real-time graphics an intrinsic component of the human/computer interface. These graphics cores accelerate the z-bu...
Karthik Ramani, Christiaan P. Gribble, Al Davis
ICPP
2003
IEEE
14 years 26 days ago
High Performance and Reliable NIC-Based Multicast over Myrinet/GM-2
Multicast is an important collective operation for parallel programs. Some Network Interface Cards (NICs), such as Myrinet, have programmable processors that can be programmed to ...
Weikuan Yu, Darius Buntinas, Dhabaleswar K. Panda
DAC
2004
ACM
14 years 8 months ago
Virtual memory window for application-specific reconfigurable coprocessors
Reconfigurable Systems-on-Chip (SoCs) on the market consist of full-fledged processors and large Field-Programmable Gate-Arrays (FPGAs). The latter can be used to implement the sy...
Miljan Vuletic, Laura Pozzi, Paolo Ienne