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ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
16 years 1 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
HPCA
2005
IEEE
15 years 9 months ago
Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems
As microprocessors become increasingly interconnected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increas...
Xuning Chen, Li-Shiuan Peh, Gu-Yeon Wei, Yue-Kai H...
ECML
2006
Springer
15 years 7 months ago
Margin-Based Active Learning for Structured Output Spaces
In many complex machine learning applications there is a need to learn multiple interdependent output variables, where knowledge of these interdependencies can be exploited to impr...
Dan Roth, Kevin Small
DASFAA
2007
IEEE
151views Database» more  DASFAA 2007»
15 years 6 months ago
The Tornado Model: Uncertainty Model for Continuously Changing Data
To support emerging database applications that deal with continuously changing (or moving) data objects (CCDOs), such as vehicles, RFIDs, and multi-stimuli sensors, one requires an...
Byunggu Yu, Seon Ho Kim, Shayma Alkobaisi, Wan D. ...
VLSID
2007
IEEE
85views VLSI» more  VLSID 2007»
16 years 4 months ago
Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective
In this paper we explore the use of a set of novel design metrics for characterizing the impact of gate oxide tunneling current in nanometer CMOS devices and perform Monte Carlo s...
Elias Kougianos, Saraju P. Mohanty