34 search results - page 5 / 7 » Characterizing the d-TLB behavior of SPEC CPU2000 benchmarks |
EUROPAR
2005
Springer
14 years 4 months ago
2005
Springer
Most programs are repetitive, meaning that some parts of a program are executed more than once. As a result, a number of phases can be extracted in which each phase exhibits simila...
ISCA
1995
IEEE
14 years 2 months ago
1995
IEEE
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
DAC
2003
ACM
14 years 4 months ago
2003
ACM
The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved perfo...
ISCA
2002
IEEE
14 years 3 months ago
2002
IEEE
The importance of the Translation Lookaside Buffer (TLB) on system performance is well known. There have been numerous prior efforts addressing TLB design issues for cutting down ...
CGO
2007
IEEE
14 years 5 months ago
2007
IEEE
Modern memory systems play a critical role in the performance of applications, but a detailed understanding of the application behavior in the memory system is not trivial to atta...