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CODES
2004
IEEE
13 years 11 months ago
A novel deadlock avoidance algorithm and its hardware implementation
This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provi...
Jaehwan Lee, Vincent John Mooney III
CP
2006
Springer
13 years 11 months ago
Stochastic Allocation and Scheduling for Conditional Task Graphs in MPSoCs
This paper describes a complete and efficient solution to the stochastic allocation and scheduling for Multi-Processor System-on-Chip (MPSoC). Given a conditional task graph charac...
Michele Lombardi, Michela Milano
IEEEHPCS
2010
13 years 6 months ago
Reducing memory requirements of stream programs by graph transformations
Stream languages explicitly describe fork-join parallelism and pipelines, offering a powerful programming model for many-core Multi-Processor Systems on Chip (MPSoC). In an embedd...
Pablo de Oliveira Castro, Stéphane Louise, ...
TC
2008
13 years 8 months ago
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
Assaf Shacham, Keren Bergman, Luca P. Carloni
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
14 years 1 months ago
eMICAM a New Generation of Active DNA Chip with in Situ Electrochemical Detection
Most of the DNA chips available on the market are based on external or internal optical detection (fluorescence or chemiluminescence) and need a bulky chip reader (optics, laser, ...
Raymond Campagnolo