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ICETET
2009
IEEE
14 years 2 months ago
Low Energy Tree Based Network on Chip Architectures Using Homogeneous Routers for Bandwidth and Latency Constrained Multimedia A
Abstract— Design of Network on chip architectures for multimedia applications is being widely studied. This involves design decisions at various levels of hierarchy. Topology des...
Deepak Majeti, Aditya Pasalapudi, Kishore Yalamanc...
EUROPAR
2007
Springer
13 years 12 months ago
Optimizing Chip Multiprocessor Work Distribution Using Dynamic Compilation
How can sequential applications benefit from the ubiquitous next generation of chip multiprocessors (CMP)? Part of the answer may be a dynamic execution environment that automatica...
Jisheng Zhao, Matthew Horsnell, Ian Rogers, Andrew...
DATE
2000
IEEE
110views Hardware» more  DATE 2000»
14 years 13 days ago
A BIST Scheme for On-Chip ADC and DAC Testing
In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measurin...
Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng
ICRA
2000
IEEE
106views Robotics» more  ICRA 2000»
14 years 12 days ago
Toward Biomorphic Control Using Custom aVLSI CPG Chips
The locomotor controller for walking, running, swimming, and flying animals is based on a Central Pattern Generator (CPG). Models of CPGs as systems of coupled non-linear oscillato...
M. Anthony Lewis, Ralph Etienne-Cummings, Avis H. ...
FPL
2008
Springer
116views Hardware» more  FPL 2008»
13 years 9 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...