A BIST Scheme for On-Chip ADC and DAC Testing

In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measuring the DNL and INL of the converters. We validate the scheme with software simulation—5% LSB (least significant bit) test accuracy can be achieved in the presence of reasonable analog imperfection.

• Type: Conference
• Year: 2000
• Where: DATE
• Authors: Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng
• Keywords: DATE 2000, Hardware, Least Significant Bit, Reasonable Analog Imperfection, Testing Onchip Ad