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VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
14 years 8 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
ICCD
2004
IEEE
122views Hardware» more  ICCD 2004»
14 years 4 months ago
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...
Krishnan Srinivasan, Karam S. Chatha, Goran Konjev...
DATE
2002
IEEE
89views Hardware» more  DATE 2002»
14 years 29 days ago
A Hierarchical Test Scheme for System-On-Chip Designs
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pi...
ESTIMEDIA
2006
Springer
13 years 11 months ago
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks
Efficient and deadlock-free routing is critical to the performance of networks-on-chip. In this paper we present an approach that can be coupled to any adaptive routing algorithm ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
GLVLSI
2008
IEEE
183views VLSI» more  GLVLSI 2008»
13 years 9 months ago
An analytical model for the upper bound on temperature differences on a chip
The main contribution of this work is an analytical model for finding the upper bound on the temperature difference among various locations on the die. The proposed model can be u...
Shervin Sharifi, Tajana Simunic Rosing