56 search results - page 6 / 12 » Chip and PIN is Broken |
FCCM
1997
IEEE
14 years 2 days ago
1997
IEEE
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
DSD
2009
IEEE
14 years 2 months ago
2009
IEEE
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
ET
2002
13 years 7 months ago
2002
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...
JETC
2008
13 years 6 months ago
2008
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a severe issue in to...
WIS
2004
13 years 9 months ago
2004
We envision an environment where humans communicate directly with computers without additional authentication inputs like passwords, passphrases, PINs (Personal Identification Num...