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» ChipViz : Visualizing Memory Chip Test Data
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ISCA
2007
IEEE
161views Hardware» more  ISCA 2007»
14 years 1 months ago
Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors
We explore the emerging application area of physics-based simulation for computer animation and visual special effects. In particular, we examine its parallelization potential and...
Christopher J. Hughes, Radek Grzeszczuk, Eftychios...
COGSCI
2010
234views more  COGSCI 2010»
13 years 7 months ago
High Regularities in Eye-Movement Patterns Reveal the Dynamics of the Visual Working Memory Allocation Mechanism
With only two to five slots of visual working memory (VWM), humans are able to quickly solve complex visual problems to near optimal solutions. To explain the paradox between tigh...
Xiaohui Kong, Christian D. Schunn, Garrick L. Wall...
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 1 months ago
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
HIPEAC
2005
Springer
14 years 27 days ago
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Abstract. Power efficiency has become a key design trade-off in embedded system designs. For system-on-a-chip embedded systems, an external bus interconnects embedded processor co...
Ke Ning, David R. Kaeli
ARC
2012
Springer
280views Hardware» more  ARC 2012»
12 years 3 months ago
Scalable Memory Hierarchies for Embedded Manycore Systems
As the size of FPGA devices grows following Moore’s law, it becomes possible to put a complete manycore system onto a single FPGA chip. The centralized memory hierarchy on typica...
Sen Ma, Miaoqing Huang, Eugene Cartwright, David L...