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ISLPED
1996
ACM
72views Hardware» more  ISLPED 1996»
14 years 1 days ago
Simultaneous buffer and wire sizing for performance and power optimization
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions...
Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung
EURODAC
1994
IEEE
186views VHDL» more  EURODAC 1994»
14 years 1 days ago
Algorithms for a switch module routing problem
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...
Shashidhar Thakur, D. F. Wong, S. Muthukrishnan
SPDP
1993
IEEE
14 years 19 hour ago
Fast Rehashing in PRAM Emulations
In PRAM emulations, universal hashing is a well-known method for distributing the address space among memory modules. However, if the memory access patterns of an application ofte...
J. Keller
COCO
1994
Springer
89views Algorithms» more  COCO 1994»
14 years 6 hour ago
Relationships Among PL, #L, and the Determinant
Recent results by Toda, Vinay, Damm, and Valiant have shown that the complexity of the determinant is characterized by the complexity of counting the number of accepting computati...
Eric Allender, Mitsunori Ogihara
ECOOP
1993
Springer
14 years 4 hour ago
Type Inference of SELF
Abstract. We have designed and implemented a type inference algorithm for the Self language. The algorithm can guarantee the safety and disambiguity of message sends, and provide u...
Ole Agesen, Jens Palsberg, Michael I. Schwartzbach