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PARLE
1987
14 years 1 months ago
Emulating Digital Logic using Transputer Networks (very High Parallelism = Simplicity = Performance)
Modern VLSI technology has changed the economic rules by which the balance between processing power, memory and communications is decided in computing systems. This will have a pr...
Peter H. Welch
TCAD
1998
95views more  TCAD 1998»
13 years 9 months ago
High-precision interconnect analysis
— Integrated circuits have evolved to a stage where interconnections significantly limit their performance and functional complexity. We introduce a set of tools to perform high...
Rui Martins, Wolfgang Pyka, Rainer Sabelka, Siegfr...
RTCSA
2006
IEEE
14 years 4 months ago
Instruction Scheduling with Release Times and Deadlines on ILP Processors
ILP (Instruction Level Parallelism) processors are being increasingly used in embedded systems. In embedded systems, instructions may be subject to timing constraints. An optimisi...
Hui Wu, Joxan Jaffar, Jingling Xue
COCO
2005
Springer
123views Algorithms» more  COCO 2005»
14 years 3 months ago
If NP Languages are Hard on the Worst-Case Then It is Easy to Find Their Hard Instances
We prove that if NP ⊆ BPP, i.e., if SAT is worst-case hard, then for every probabilistic polynomial-time algorithm trying to decide SAT, there exists some polynomially samplable ...
Dan Gutfreund, Ronen Shaltiel, Amnon Ta-Shma
CC
2007
Springer
121views System Software» more  CC 2007»
13 years 10 months ago
If NP Languages are Hard on the Worst-Case, Then it is Easy to Find Their Hard Instances
We prove that if NP ⊆ BPP, i.e., if SAT is worst-case hard, then for every probabilistic polynomial-time algorithm trying to decide SAT, there exists some polynomially samplable ...
Dan Gutfreund, Ronen Shaltiel, Amnon Ta-Shma