Sciweavers

96 search results - page 4 / 20
» Circuit modeling for practical many-core architecture design...
Sort
View
VLSID
2008
IEEE
149views VLSI» more  VLSID 2008»
14 years 8 months ago
NBTI Degradation: A Problem or a Scare?
Negative Bias Temperature Instability (NBTI) has been identified as a major and critical reliability issue for PMOS devices in nano-scale designs. It manifests as a negative thres...
Kewal K. Saluja, Shriram Vijayakumar, Warin Sootka...
CSUR
2006
147views more  CSUR 2006»
13 years 7 months ago
A survey of research and practices of Network-on-chip
resents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. ...
Tobias Bjerregaard, Shankar Mahadevan
ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
14 years 4 months ago
Robust system level design with analog platforms
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
DAC
2004
ACM
14 years 8 months ago
Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions
This paper presents the Quantum-Dot Cellular Automata (QCA) physical design problem, in the context of the VLSI physical design problem. The problem is divided into three subprobl...
Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dy...
DFT
1998
IEEE
78views VLSI» more  DFT 1998»
13 years 12 months ago
A System for Evaluating On-Line Testability at the RT-level
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
Silvia Chiusano, Fulvio Corno, Matteo Sonza Reorda...