3395 search results - page 133 / 679 » Circuit-aware architectural simulation |
126
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DAC
1999
ACM
15 years 9 months ago
1999
ACM
: In this work we propose a technique for spatial and temporal partitioning of a logic circuit based on the nodes activity computed by using a simulation at an higher level of ion....
108
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DAC
2005
ACM
16 years 5 months ago
2005
ACM
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
138
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SIES
2009
IEEE
15 years 11 months ago
2009
IEEE
—The performance estimation of complex multi-processor systems-on-chip (MPSoC) in a reasonable amount of time and with a good accuracy becomes more and more challenging due to th...
142
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IPPS
2007
IEEE
15 years 11 months ago
2007
IEEE
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
134
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ICPR
2000
IEEE
16 years 5 months ago
2000
IEEE
Nowadays, every industry's goal is to improve their manufacturingprocesses and to increase their cadence of production, in order to be competitive. This goal usually implies ...