3395 search results - page 618 / 679 » Circuit-aware architectural simulation |
EUROMICRO
1999
IEEE
14 years 15 days ago
1999
IEEE
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
EUROMICRO
1999
IEEE
14 years 15 days ago
1999
IEEE
This research proposes a selective compressed memory system (SCMS) focusing on a compressed cache architecture, in which only data blocks with good compression efficiency are comp...
SIGGRAPH
1999
ACM
14 years 15 days ago
1999
ACM
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...
HPCA
1999
IEEE
14 years 15 days ago
1999
IEEE
This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/ execute decoupling and simultaneous multithreading. We investigate how b...
ICCD
1999
IEEE
14 years 14 days ago
1999
IEEE
This paper describes a core-customization process of a CISC processor core for a given application program. It aims at the power reduction in the CISC processor core by fully util...