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» Circuits, Pebbling and Expressibility
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FCT
2009
Springer
14 years 3 months ago
Small-Space Analogues of Valiant's Classes
In the uniform circuit model of computation, the width of a boolean circuit exactly characterises the “space” complexity of the computed function. Looking for a similar relatio...
Meena Mahajan, B. V. Raghavendra Rao
FCCM
1998
IEEE
148views VLSI» more  FCCM 1998»
14 years 26 days ago
JHDL - An HDL for Reconfigurable Systems
JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard pro...
Peter Bellows, Brad L. Hutchings
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
14 years 3 days ago
Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
Randal E. Bryant
SBCCI
2006
ACM
126views VLSI» more  SBCCI 2006»
14 years 2 months ago
Power constrained design optimization of analog circuits based on physical gm/ID characteristics
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
Alessandro Girardi, Sergio Bampi
EMSOFT
2004
Springer
14 years 10 days ago
A methodology for generating verified combinatorial circuits
High-level programming languages offer significant expressivity but provide little or no guarantees about resource use. Resourcebounded languages -- such as hardware-description l...
Oleg Kiselyov, Kedar N. Swadi, Walid Taha