Sciweavers

6432 search results - page 1279 / 1287
» Classic Mechanism Design
Sort
View
TC
2011
13 years 1 months ago
Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
Thomas J. Ashby, Pedro Diaz, Marcelo Cintra
INFOCOM
2011
IEEE
12 years 11 months ago
To preempt or not: Tackling bid and time-based cheating in online spectrum auctions
—Online spectrum auctions offer ample flexibility for bidders to request and obtain spectrum on-the-fly. Such flexibility, however, opens up new vulnerabilities to bidder mani...
Lara B. Deek, Xia Zhou, Kevin C. Almeroth, Haitao ...
ISCA
2011
IEEE
270views Hardware» more  ISCA 2011»
12 years 11 months ago
Sampling + DMR: practical and low-overhead permanent fault detection
With technology scaling, manufacture-time and in-field permanent faults are becoming a fundamental problem. Multi-core architectures with spares can tolerate them by detecting an...
Shuou Nomura, Matthew D. Sinclair, Chen-Han Ho, Ve...
ASPLOS
2011
ACM
12 years 11 months ago
MemScale: active low-power modes for main memory
Main memory is responsible for a large and increasing fraction of the energy consumed by servers. Prior work has focused on exploiting DRAM low-power states to conserve energy. Ho...
Qingyuan Deng, David Meisner, Luiz E. Ramos, Thoma...
BMCBI
2011
12 years 11 months ago
A user-friendly web portal for T-Coffee on supercomputers
Background: Parallel T-Coffee (PTC) was the first parallel implementation of the T-Coffee multiple sequence alignment tool. It is based on MPI and RMA mechanisms. Its purpose is t...
Josep Rius Torrento, Fernando Cores, Francesc Sols...
« Prev « First page 1279 / 1287 Last » Next »