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DFT
2009
IEEE
189views VLSI» more  DFT 2009»
14 years 4 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
ATAL
2006
Springer
14 years 1 months ago
Reducing costly information acquisition in auctions
Most research on auctions assumes that potential bidders have private information about their willingness to pay for the item being auctioned, and that they use this information s...
Kate Larson
IFIPTM
2009
127views Management» more  IFIPTM 2009»
13 years 7 months ago
A Risk Based Approach to Limit the Effects of Covert Channels for Internet Sensor Data Aggregators for Sensor Privacy
Effective defense against Internet threats requires data on global real time network status. Internet sensor networks provide such real time network data. However, an organization...
Camilo H. Viecco, L. Jean Camp
ET
2002
90views more  ET 2002»
13 years 9 months ago
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...

Presentation
494views
14 years 8 months ago
Online Mechanisms without Money for Assignment of Objects to Strategic Agents
Presented at First Electrical Science Divisional Symposium, Indian Institute of Science. This is joint work with Prof David Parkes, Harvard University.
Sujit Gujar