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» Clock Synchronization with Bounded Global and Local Skew
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ASYNC
2002
IEEE
115views Hardware» more  ASYNC 2002»
14 years 15 days ago
Point to Point GALS Interconnect
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
George S. Taylor, Simon W. Moore, Robert D. Mullin...
ASPDAC
2001
ACM
104views Hardware» more  ASPDAC 2001»
13 years 11 months ago
Optimal spacing and capacitance padding for general clock structures
Clock-tuning has been classified as important but tough tasks due to the non-convex nature caused by the skew requirements. As a result, all existing mathematical programming appr...
Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen
ASPDAC
2008
ACM
115views Hardware» more  ASPDAC 2008»
13 years 9 months ago
An optimal algorithm for sizing sequential circuits for industrial library based designs
In this paper, we propose an optimal gate sizing and clock skew optimization algorithm for globally sizing synchronous sequential circuits. The number of constraints and variables ...
Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Che...
ICDCS
2009
IEEE
14 years 4 months ago
FLASH: Fine-Grained Localization in Wireless Sensor Networks Using Acoustic Sound Transmissions and High Precision Clock Synchro
Sensor localization in wireless sensor networks is an important component of many applications. Previous work has demonstrated how localization can be achieved using various metho...
Evangelos Mangas, Angelos Bilas
ICCD
2005
IEEE
121views Hardware» more  ICCD 2005»
14 years 4 months ago
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
Bradley R. Quinton, Mark R. Greenstreet, Steven J....