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» Clock distribution using multiple voltages
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SLIP
2009
ACM
14 years 3 months ago
Predicting the worst-case voltage violation in a 3D power network
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shaya...
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
14 years 2 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
SASP
2008
IEEE
164views Hardware» more  SASP 2008»
14 years 3 months ago
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications
This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The proces...
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishito...
ISCAS
2005
IEEE
108views Hardware» more  ISCAS 2005»
14 years 2 months ago
Noise coupling in multi-voltage power distribution systems with decoupling capacitors
— Multiple power supply voltages are often used in modern high performance ICs such as microprocessors to decrease power consumption without affecting circuit speed. The system o...
Mikhail Popovich, Eby G. Friedman
VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
14 years 9 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan