90 search results - page 8 / 18 » Clock distribution using multiple voltages |
PLDI
2003
ACM
14 years 2 months ago
2003
ACM
With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-t...
EDCC
1999
Springer
14 years 1 months ago
1999
Springer
In this paper we present a new fault tolerant clock synchronization algorithm called the Fault Tolerant Daisy Chain algorithm. It is intended for internal clock synchronization of...
ISCA
2002
IEEE
14 years 1 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
DAC
2005
ACM
13 years 10 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
GLVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
Dynamic voltage scaling (DVS) for real-time systems has been extensively studied to save energy. Previous studies consider the probabilistic distributions of tasks’ execution ti...