205 search results - page 23 / 41 » Clock gating architectures for FPGA power reduction |
DAC
2010
ACM
13 years 8 months ago
2010
ACM
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...
VLSID
2007
IEEE
14 years 11 months ago
2007
IEEE
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...
CSREAESA
2004
14 years 6 days ago
2004
Discrete wavelet transform has been incorporated as part of the JPEG2000 image compression standard and is being deployed in various portable consumer products. This raises the in...
DAC
2000
ACM
14 years 11 months ago
2000
ACM
This paper presents a novel run-time dynamic voltage scaling scheme for low-power real-time systems. It employs software feedback control of supply voltage, which is applicable to...
ISCAS
2008
IEEE
14 years 5 months ago
2008
IEEE
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...