96 search results - page 4 / 20 » Clock-Aware Placement for FPGAs |
FPL
2006
Springer
13 years 11 months ago
2006
Springer
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
In a typical design
ow, the design may be altered slightly several times after the initial design cycle according to minor changes in the design speci cation either as a result o...
FPL
2005
Springer
14 years 26 days ago
2005
Springer
Current FPGA placement algorithms estimate the routability of a placement using architecture-specific metrics. The shortcoming of using architecture-specific routability estimates ...
FPGA
1995
ACM
13 years 11 months ago
1995
ACM
Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused...
FPL
2010
Springer
13 years 5 months ago
2010
Springer
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...