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INTEGRATION
2007
95views more  INTEGRATION 2007»
13 years 7 months ago
Wire shaping of RLC interconnects
The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tap...
Magdy A. El-Moursy, Eby G. Friedman
PVLDB
2010
166views more  PVLDB 2010»
13 years 6 months ago
Complex Event Detection at Wire Speed with FPGAs
Complex event detection is an advanced form of data stream processing where the stream(s) are scrutinized to identify given event patterns. The challenge for many complex event pr...
Louis Woods, Jens Teubner, Gustavo Alonso
GLVLSI
2009
IEEE
123views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Power efficient tree-based crosslinks for skew reduction
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G...
USS
2004
13 years 9 months ago
TIED, LibsafePlus: Tools for Runtime Buffer Overflow Protection
Buffer overflow exploits make use of the treatment of strings in C as character arrays rather than as first-class objects. Manipulation of arrays as pointers and primitive pointer...
Kumar Avijit, Prateek Gupta, Deepak Gupta
ISCAS
2003
IEEE
77views Hardware» more  ISCAS 2003»
14 years 27 days ago
Inductive interconnect width optimization for low power
The width of an interconnect line a ects the total power consumed by a circuit. A tradeo exists, however, between the dynamic power and the short-circuit power in determining the ...
Magdy A. El-Moursy, Eby G. Friedman