Power efficient tree-based crosslinks for skew reduction

Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutions significantly increase the dissipated power, whereas existing link based methods only address skew caused by variations and do not consider power consumption. The power dissipated by the inserted crosslinks within a buffered clock tree is investigated in this paper, and is shown to be a strong function of the resistance and capacitance of the crosslink. A crosslink may be power efficient despite the presence of short-circuit currents caused by multiple drivers in a non-tree clock network. The power characteristics of crosslink size and placement are also discussed, showing that the crosslink is best placed as close as possible to the target leaves of the tree. Crosslink insertion as both an alternative and complement to buffer sizing for low power skew reduction is also considered. Categories and Subject D...

• Type: Conference
• Year: 2009
• Where: GLVLSI
• Authors: Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman
• Keywords: Crosslink, Crosslink Size, Dissipated Power, GLVLSI 2009, VLSI