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ASPDAC
2004
ACM
129views Hardware» more  ASPDAC 2004»
14 years 29 days ago
Instruction buffering exploration for low energy VLIWs with instruction clusters
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
Tom Vander Aa, Murali Jayapala, Francisco Barat, G...
PLDI
2003
ACM
14 years 23 days ago
Region-based hierarchical operation partitioning for multicluster processors
Clustered architectures are a solution to the bottleneck of centralized register files in superscalar and VLIW processors. The main challenge associated with clustered architectu...
Michael L. Chu, Kevin Fan, Scott A. Mahlke
ISCA
2003
IEEE
93views Hardware» more  ISCA 2003»
14 years 24 days ago
Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors
This work examines dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue wid...
Ravi Bhargava, Lizy Kurian John
TCAD
2002
118views more  TCAD 2002»
13 years 7 months ago
Application-specific clustered VLIW datapaths: early exploration on a parameterized design space
Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level para...
Viktor S. Lapinskii, Margarida F. Jacome, Gustavo ...
IEEEPACT
2002
IEEE
14 years 13 days ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany