Sciweavers

398 search results - page 67 / 80
» Code Cache Management Schemes for Dynamic Optimizers
Sort
View
ISCA
2011
IEEE
238views Hardware» more  ISCA 2011»
13 years 23 days ago
Rebound: scalable checkpointing for coherent shared memory
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
Rishi Agarwal, Pranav Garg, Josep Torrellas
ICPP
2008
IEEE
14 years 3 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...
CISS
2008
IEEE
14 years 3 months ago
Appropriate control of wireless networks with flow level dynamics
Abstract— We consider the network control problem for wireless networks with flow level dynamics under the general k-hop interference model. In particular, we investigate the co...
Long Le, Ravi R. Mazumdar
BTW
2007
Springer
154views Database» more  BTW 2007»
14 years 3 months ago
Integrating Query-Feedback Based Statistics into Informix Dynamic Server
: Statistics that accurately describe the distribution of data values in the columns of relational tables are essential for effective query optimization in a database management sy...
Alexander Behm, Volker Markl, Peter J. Haas, Kesha...
IPPS
2007
IEEE
14 years 3 months ago
Analysis of a Computational Biology Simulation Technique on Emerging Processing Architectures
1 Multi-paradigm, multi-threaded and multi-core computing devices available today provide several orders of magnitude performance improvement over mainstream microprocessors. These...
Jeremy S. Meredith, Sadaf R. Alam, Jeffrey S. Vett...