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MAM
2006
124views more  MAM 2006»
13 years 9 months ago
Design optimization and space minimization considering timing and code size via retiming and unfolding
The increasingly complicated DSP processors and applications with strict timing and code size constraints require design automation tools to consider multiple optimizations such a...
Qingfeng Zhuge, Chun Xue, Zili Shao, Meilin Liu, M...
HIPEAC
2010
Springer
13 years 11 months ago
Offload - Automating Code Migration to Heterogeneous Multicore Systems
We present Offload, a programming model for offloading parts of a C++ application to run on accelerator cores in a heterogeneous multicore system. Code to be offloaded is enclosed ...
Pete Cooper, Uwe Dolinsky, Alastair F. Donaldson, ...
MICRO
1996
IEEE
173views Hardware» more  MICRO 1996»
14 years 1 months ago
Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results
The Java bytecode language is emerging as a software distribution standard. With major vendors committed to porting the Java run-time environment to their platforms, programs in J...
Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, Wen-mei ...
IEEEPACT
2002
IEEE
14 years 1 months ago
An Evaluation of Data-Parallel Compiler Support for Line-Sweep Applications
Data parallel compilers have long aimed to equal the performance of carefully hand-optimized parallel codes. For tightly-coupled applications based on line sweeps, this goal has b...
Daniel G. Chavarría-Miranda, John M. Mellor...
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
14 years 6 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda