Hardware libraries: An architecture for economic acceleration in soft multi-core environments

In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to achieve a significant speedup over software. The increased design constraints from power density and signal delay have shifted processor architectures in general towards multi-core designs. The migration to multicore designs introduces the possibility of sharing hardware accelerators between cores. In this paper, we propose the concept of a hardware library, which is a pool of accelerated functions that are accessible by multiple cores. We find that sharing provides significant reductions in the area, logic usage and leakage power required for hardware acceleration. Contention for these units may exist in certain cases; however, the savings in terms of chip area are more appealing to many applications, particularly the embedded domain. We study the performance implications for our proposal using various mu...

• Type: Conference
• Year: 2007
• Where: ICCD
• Authors: David Meisner, Sherief Reda
• Keywords: Hardware, Hardware Accelerators, ICCD 2007, Single Processor Architectures, Various Multi-core Arrangements