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143
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VLSISP
2008
132views more  VLSISP 2008»
15 years 2 months ago
Scenario Selection and Prediction for DVS-Aware Scheduling of Multimedia Applications
Modern multimedia applications usually have real-time constraints and they are implemented using application-domain specific embedded processors. Dimensioning a system requires acc...
Stefan Valentin Gheorghita, Twan Basten, Henk Corp...
124
Voted
RTCSA
2007
IEEE
15 years 8 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
133
Voted
ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
14 years 12 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...
130
Voted
SEUS
2010
IEEE
15 years 17 days ago
Error Detection Rate of MC/DC for a Case Study from the Automotive Domain
Chilenski and Miller [1] claim that the error detection probability of a test set with full modified condition/decision coverage (MC/DC) on the system under test converges to 100%...
Susanne Kandl, Raimund Kirner
ECRTS
2006
IEEE
15 years 8 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut