Sciweavers

966 search results - page 16 / 194
» Code Generation for Embedded Processors
Sort
View
CASES
2003
ACM
14 years 24 days ago
Compiler optimization and ordering effects on VLIW code compression
Code size has always been an important issue for all embedded applications as well as larger systems. Code compression techniques have been devised as a way of battling bloated co...
Montserrat Ros, Peter Sutton
VLSISP
2010
97views more  VLSISP 2010»
13 years 5 months ago
Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories
Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
ISCAS
2003
IEEE
89views Hardware» more  ISCAS 2003»
14 years 24 days ago
Systematic test program generation for SoC testing using embedded processor
Mohammad H. Tehranipour, Mehrdad Nourani, Seid Meh...
DATE
2004
IEEE
138views Hardware» more  DATE 2004»
13 years 11 months ago
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructio...
Juan L. Aragón, Dan Nicolaescu, Alexander V...
ISCC
2005
IEEE
120views Communications» more  ISCC 2005»
14 years 1 months ago
Modular Reference Implementation of an IP-DSLAM
We describe a modular reference implementation of an IPbased DSL access multiplexer (DSLAM). We identify deployment trends and primary tasks a future DSLAM has to offer. The imple...
Christian Sauer, Matthias Gries, Sören Sonnta...