245 search results - page 39 / 49 » Code Optimization Techniques for Embedded DSP Microprocessor... |
FCCM
2004
IEEE
13 years 11 months ago
2004
IEEE
The development of turbo codes has allowed for nearShannon limit information transfer in modern communication systems. Although turbo decoding is viewed as superior to alternate d...
MICRO
2000
IEEE
13 years 7 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
CHES
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. This paper discusses the state-of-the-art fast software implementation of block ciphers on Intel’s new microprocessor Core2, particularly concentrating on “bitslice i...
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
ICCCN
2008
IEEE
14 years 2 months ago
2008
IEEE
— Energy management is the key issue in the design and operation of wireless network applications like sensor networks, pervasive computing and ubiquitous computing where the net...