159 search results - page 27 / 32 » Code Synthesis for Timed Automata |
SIES
2007
IEEE
14 years 1 months ago
2007
IEEE
— High level synthesis is one of the next major steps to improve the hw/sw co-design process. The advantages of high nthesis are two-fold. At first the level of abstraction is r...
DAGSTUHL
2004
13 years 9 months ago
2004
Abstract. Synchronous programs may contain cyclic signal interdependencies. This prohibits a static scheduling, which limits the choice of available compilation techniques for such...
ASE
2005
13 years 7 months ago
2005
Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...
CODES
2003
IEEE
14 years 25 days ago
2003
IEEE
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
FPL
2004
Springer
14 years 28 days ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...