Sciweavers

272 search results - page 15 / 55
» Code Transformations to Improve Memory Parallelism
Sort
View
IPPS
2007
IEEE
14 years 2 months ago
Model-Guided Empirical Optimization for Multimedia Extension Architectures: A Case Study
Compiler technology for multimedia extensions must effectively utilize not only the SIMD compute engines but also the various levels of the memory hierarchy: superword registers,...
Chun Chen, Jaewook Shin, Shiva Kintali, Jacqueline...
DEBS
2008
ACM
13 years 10 months ago
Speculative out-of-order event processing with software transaction memory
In event stream applications, events flow through a network of components that perform various types of operations, e.g., filtering, aggregation, transformation. When the operatio...
Andrey Brito, Christof Fetzer, Heiko Sturzrehm, Pa...
ICCD
2006
IEEE
97views Hardware» more  ICCD 2006»
14 years 5 months ago
Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Sa...
DAC
2007
ACM
14 years 9 months ago
Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification
Programming multi-processor systems-on-chip (MPSoC) involves partitioning and mapping of sequential reference code onto multiple parallel processing elements. The immense potentia...
Pramod Chandraiah, Rainer Dömer
IEEEPACT
2009
IEEE
14 years 3 months ago
Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling
—Analytical models have been used to estimate optimal values for parameters such as tile sizes in the context of loop nests. However, important algorithms such as fast Fourier tr...
Basilio B. Fraguela, Yevgen Voronenko, Markus P&uu...